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74HC595 Series Datasheet

74HC595

High-Speed Si-gate CMOS Devices

The 74HC595 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.The 74HC595 are 8-stage serial shift registers with a storage register and 3-state outputs. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW.

74HC595 Data sheet.pdf

74HC595 Pin Configuration and Function

Pin Number	Pin Name	Description
1,2,3,4,5,6,7	Q1 to Q7	parallel data output 1 to 7
8	Ground	ground (o v)
9	Q7S	serial data output
10	MR	master reset (active Low)
11	SHCP	shift register clock input
12	STCP	storage register clock input
13	OE	output enable input (active Low)
14	DS	serial data input
15	Q0	parallel data output 0
16	Vcc	supply voltage