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74LS148 Series Datasheet

74LS148

Logic ICs

These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is encoded. The ’148 and ’LS148 devices encode eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry. For all types, data inputs and outputs are active at the low logic level.

74LS148 Pin Configuration and Function

74ls148.jpg

Pin No

Function

Description

10, 11, 12, 13, 1, 2, 3, 4

0 to 7

Encoding input terminal (active low)

5

EI

Strobe input terminal (active low)

9, 7, 6

A0 to A1

The three-bit binary coded output signal   is the coded output terminal (active low)

8

GND

GROUND

14

GS

The output terminal of chip-first   encoding is the widening terminal (active low)

15

E0

Strobe output, even if it can output

16

Vcc

voltage


74LS148 Series Datasheet

Part No
Picture
Manufacturer
Package
Description
Datasheet
SN74LS148D
SN74LS148D
TI
SOIC, PDIP

TEXAS INSTRUMENTS SN74LS148D Priority Encoder, LS Family, 3 Output, 8mA, 4.75V to 5.25V, SOIC-16

SN74LS148N
SN74LS148N
TI
DIP

TEXAS INSTRUMENTS SN74LS148N Priority Encoder, LS Family, 5 Output, 8mA, 4.75V to 5.25V, DIP-16

SN74LS148DR
SN74LS148DR
TI
SOIC, PDIP

Encoder 8-to-3 Priority Bipolar 16Pin SOIC T/R

SN74LS148DG4
SN74LS148DG4
TI
SOIC, PDIP

Encoder 8-to-3 Priority Bipolar 16Pin SOIC Tube

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